The present invention relates to a single-event upset (SEU) hardened integrated circuit, and, more particularly to an SEU hardened asymmetric bi-stable CMOS latch wherein when the latch is powered-up it is set to a predetermined state.
In combinational logic circuits, data latches are susceptible to single-event upsets (SEUs). The radiation hardness requirements imposed on systems used in space and strategic applications necessitate that the data latches in logic chips be SEU hardened. Data latches are used in latch chains and as separate logic gates for data manipulation in storage. Several data latches may lie in critical signal paths, so consequently, data latch hardening techniques must preserve latch speed. Data latches outside the critical signal paths do not require as high performance level as data latches which are located in a critical signal path. The hardness against SEUs (i.e., ability to withstand single particle hits without logic upset) may be achieved by virtue of the design of the data latch or through the fabrication process or a combination of both. Design hardening offers the most practical approach to gaining SEU protection without seriously degrading latch performance.
Programmable logic circuits (e.g., field programmable gate arrays (FPGAs)) are used widely in digital system designs. Programmable logic circuits are comprised of an array of unconnected logic elements that can be programmed (i.e., configured) to form a complex logic circuit to accomplish a prescribed function. Most programmable logic circuits employ fuses, anti-fuses, or custom designed metal mask levels to configure the logic elements. Once configured, the resulting logic circuit design is permanent (xe2x80x9cfirmxe2x80x9d) and cannot be altered later.
Reconfigurable (or xe2x80x9creprogrammablexe2x80x9d) logic circuits can be changed to form a different logic function on demand. Reconfigurable logic circuits generally employ a bi-stable data storage clement (e.g., a data latch or an SRAM cell) within which the logic configuration data is stored. Depending on whether a logical xe2x80x9conexe2x80x9d or logical xe2x80x9czeroxe2x80x9d data is stored in the data storage element, the logic, configuration interface gate or device connected to the data storage element""s output is either on or off. In that way, blocks of previously unconnected logic elements are connected and the logic circuit is configured. Selectively changing the data stored in some of the data storage elements allows one to reconfigure the logic circuits when desired. Reconfigurable logic circuits offer a significant advantage over one-time programmable xe2x80x9cfirmxe2x80x9d logic circuits in that the hardware can be changed even after the digital system has been deployed for many years.
There is a lot of reluctance to use reconfigurable logic circuits in space and military applications that generally must operate in stringent, noisy radiation environments. The major fear is that the logic-configuration data storage elements may be strick by a single-event upset (SEU) inducing heavy ion, upsetting the data stored, and thereby unintentionally reconfigure the logic circuit. Ways to circumvent this threat involve techniques like triple module redundancy, for example, which requires significant amounts of design and operation overhead and are never completely fool proof.
As used herein and as known in the art, complimentary MOS (CMOS) refers to integrated circuits which employ both p-channel field effect transistor devices (PFET) and n-channel field effect transistor devices (NFET) which are connected so as to provide high speed, low power dissipation, integrated circuits for logic and memory applications. The abbreviation NFET is used herein to refer to an enhancement mode n-channel field effect transistor device. Such devices are generally fabricated by forming an N-type conductivity source diffusion and N-type drain diffusion in the surface of a P-type conductivity silicon substrate. The channel region of the substrate separating the source and drain regions, is covered by a gate insulator layer and a gate electrode. An enhancement mode NFET is normally non-conducting between its source and drain and it can be switched into conduction by applying a positive potential to its gate electrode, with respect to the potential of its source.
The abbreviation PFET will be used herein to refer to an enhancement mode p-channel field effect transistor device. Such devices are generally fabricated by forming P-type conductivity source diffusion and P-type conductivity drain diffusions within an N-type conductivity diffusion called an N-well which, in turn, has been formed in the P-type semiconductor substrate for the integrated circuit. The channel region of the N-well separating the P-type source and drain diffusions is covered by the gate insulator layer and the gate electrode. An enhancement mode PFET is normally non-conducting between a source and drain when the gate-to-source potential is relatively negative, the opposite condition from that obtaining from an NFET device relative to biasing.
In steady state operation, when the gate inputs are low (approximately 0 volts) the n-channel devices are turned off (non-conducting) and the p-channel devices are turned on (conducting). When the gate inputs are high (VDD) the n-channel devices are turned on and the p-channel devices are turned off.
In one embodiment, the present invention provides a single event upset (SEU) hardened integrated circuit. The integrated circuit includes an asymmetric bi-stable CMOS latch having a first logic state and a second logic state. A supply voltage is operably coupled to the asymmetric bi-stable latch, where upon activation of the supply voltage the asymmetric bi-stable latch is always set to the first logic state.
In one aspect, the asymmetric CMOS bi-stable latch includes a first CMOS inverter and a second CMOS inverter. The second CMOS inverter is cross-coupled to the first CMOS inverter, wherein the first CMOS inverter is asymmetric with the second CMOS inverter. The first CMOS inverter includes a first data node having a first nodal capacitance, and the second CMOS inverter includes a second data node having a second nodal capacitance different from the first nodal capacitance which defines the asymmetry between the first CMOS inverter and the second CMOS inverter.
The first CMOS inverter includes a first p-channel transistor and a first n-channel transistor. The second CMOS inverter includes a second p-channel transistor and a second n-channel transistor. The drain area of the first n-channel transistor is greater than the drain area of the second n-channel transistor. In one aspect, the drain area of the first n-channel transistor is more the four times the drain area of the second n-channel transistor.
In one embodiment, the SEU hardened asymmetric bi-stable CMOS latch includes an SEU hardening component. In one aspect, the SEU hardening component is a thin film resistor. In one aspect, the asymmetric bi-stable CMOS latch includes a first CMOS inverter and a second CMOS inverter. The second CMOS inverter is cross-coupled to the first CMOS inverter via a first coupling segment and a second coupling segment. The first CMOS inverter is asymmetric with the second CMOS inverter. The SEU hardening component is a thin film resistor positioned in the first coupling segment. Optionally, the SEU hardening component may be positioned in the first coupling segment, the second coupling segment, or both the first coupling segment and second coupling segment. Preferably, the thin film resistor is a polysilicon resistor.
The asymmetric bi-stable CMOS latch is reconfigurable between the first logic state and the second logic state, and may further include a switch for switching the asymmetric bi-stable CMOS latch between the first logic state and the second logic state. In one aspect, the switch includes an n-channel transistor. The latch further includes a pulsed input signal received by the n-channel transistor for switching the asymmetric bi-stable CMOS latch from the first logic state to the second logic state.
The latch may further include a reset coupled to the asymmetric bi-stable CMOS latch, wherein the reset operates to reset the asymmetric bi-stable latch to the first logic state.
In another embodiment, the present invention provides an SEU hardened bi-stable reconfigurable latch coupled to a supply voltage. The latch has a first logic state and a second logic state. The latch includes a first inverter including a first p-channel field effect transistor, a first n-channel field effect transistor, and a first data node located between the first p-channel transistor and the first n-channel transistor. A second inverter is provided including a second p-channel field effect transistor, a second n-channel field effect transistor and a second data node located between the second p-channel field effect transistor and the second n-channel field effect transistor. The first inverter is cross-coupled to the second inverter via a first coupling segment and a second coupling segment. The first p-channel field effect transistor is symmetric with the second p-channel field effect transistor. The first data node has a first nodal capacitance and the second data node has a second nodal capacitance asymmetric with the first nodal capacitance. An SEU hardening component is operably positioned within the latch. The first p-channel field effect transistor and the second p-channel field effect transistor each have a source coupled to the supply voltage, wherein upon activation of the supply voltage the latch is always set to the first logic state.
The latch may include a switch coupled across the second n-channel field effect transistor for selectively switching the latch between the first logic state and the second logic state. In one aspect, the switch includes a third n-channel field effect transistor. The switch is responsive to an input signal for switching the latch from the first logic state to the second logic state. In one aspect, the input signal is a pulse signal. The latch may further include a reset switch for selectively resetting the latch to the first logic state. In one aspect, the reset switch includes a fourth n-channel field effect transistor coupled across the first n-channel field effect transistor.
The SEU hardening component may be a thin film resistor. In one preferred application, the thin film resistor is an intracell polysilicon resistor.
The latch may further include an output data node defined by the first p-channel field effect transistor and the first n-channel field effect transistor each having a gate coupled together. The SEU hardening component includes a polysilicon resistor located in the second cross-coupled segment between the output data node and the second data node. In one application, the SEU hardening component preferably comprises a single thin film resistor.
The first n-channel field effect transistor includes a first drain area and the second n-channel field effect transistor includes a second drain area, wherein the first drain area is greater than the second drain area. In one aspect, a switch including a third field effect transistor is positioned across the second n-channel field effect transistor for selectively switching the latch between the first logic state and the second logic state. The first n-channel field effect transistor includes a first drain area, and the second n-channel field effect transistor includes a second drain area, and the third field effect transistor includes a third drain area, wherein the first drain area is greater than the sum of the second drain area and the third drain. In one aspect, the first drain area is more that twice the sum of the second drain area and the third drain area. In one aspect, the third field effect transistor is a third n-channel field effect transistor.
The first p-channel field effect transistor and the first n-channel field effect transistor each include a gate which are tied together defining a third data node. The second p-channel field effect transistor and the second n-channel field effect transistor each include a gate which are tied together to define a fourth data node. The first coupling segment is positioned between the first data node and the fourth data node. The second coupling segment is positioned between the third data node and the second data node. The SEU hardening component includes a thin film resistor located in the first coupling segment. The SEU hardening component may further include a thin film resistor located in the second coupling segment. Alternatively, the SEU hardening component includes a single thin film resistor in the second coupling segment.
In another embodiment, the present invention provides a bi-stable reconfigurable CMOS latch coupled to a supply voltage. The latch has a first logic state and a second logic state. The latch includes a first inverter including a first p-channel field effect transistor, a first n-channel field effect transistor, and a first data node located between the first p-channel filed effect transistor and the first n-channel field effect transistor. A second inverter is provided including a second p-channel field effect transistor, a second n-channel field effect transistor and a second data node located between the second p-channel field effect transistor and the second n-channel field effect transistor. The first inverter is cross-coupled to the second inverter via a first coupling segment and a second coupling segment. The first p-channel field effect transistor is symmetric with the second p-channel field effect transistor. The first data node has a first nodal capacitance and the second data node has a second nodal capacitance asymmetric with the first nodal capacitance. The first p-channel field effect transistor and the second p-channel field effect transistor each have a source coupled to the supply voltage, wherein upon application of the supply voltage of the latch is always set to the first logic state. A switch is coupled across the second n-channel field effect transistor for selectively switching the latch between the first logic state and the second logic state.
The switch may include a third n-channel field effect transistor. The switch is responsive to an input signal for switching the latch from the first logic state to the second logic state. The latch may further include a reset switch for selectively resetting the latch to the first logic state. The reset switch may include a fourth n-channel field effect transistor coupled across the first n-channel field effect transistor.
In another embodiment, the present invention provides a single event upset (SEU) hardened circuit. The circuit includes a critical path logic circuit portion. A non-critical path logic portion is provided including an SEU hardened asymmetric bi-stable CMOS latch having a first logic state and a second logic state including an SEU hardening component. A supply voltage is operably coupled to the asymmetric bi-stable latch, wherein upon activation of the supply voltage, the asymmetric bi-stable latch is always set to the first logic state.
In another embodiment, the present invention provides a field programmable gate array. The field programmable gate array includes a critical path logic circuit portion including an array of logical devices. A non-critical path logic circuit portion is provided including an asymmetric bi-stable CMOS latch having a first logic state and a second logic state. A supply voltage is operably coupled to the asymmetric bi-stable latch, wherein upon activation of the supply voltage the asymmetric bi-stable latch is always set to the first logic state.
The circuit asymmetric bi-stable CMOS latch further includes a first CMOS inverter and a second CMOS inverter cross-coupled to the first CMOS inverter. The first CMOS inverter is asymmetric with the second CMOS inverter.
The first CMOS inverter includes a first data node having a first nodal capacitance, and a second CMOS inverter includes a second data node having a second nodal capacitance different from the first nodal capacitance which defines the asymmetry between the first CMOS inverter and the second CMOS inverter. In one aspect, the first CMOS inverter includes a first p-channel transistor and a first n-channel transistor, and the second CMOS inverter includes a second p-channel transistor and a second n-channel transistor, wherein the drain area of the first n-channel transistor is greater than the drain area of the second n-channel transistor. In one aspect, the asymmetric bi-stable CMOS latch is SEU hardened.
In one aspect, the asymmetric bi-stable CMOS latch includes a first CMOS inverter and a second CMOS inverter. The second CMOS inverter is cross-coupled to the first CMOS inverter by a first coupling segment and a second coupling segment. The first CMOS inverter is asymmetric with the second CMOS inverter. The asymmetric bi-stable CMOS latch includes an SEU hardening component, wherein the SEU hardening component is a resistor positioned in the first coupling segment.
The array of logical devices may include a first logic device, and further wherein the asymmetric bi-stable latch is operably coupled to the first logic device for controlling activation of the first logic device.
In another embodiment, the present invention provides a power failure detector. The power failure detector includes an asymmetric bi-stable CMOS latch having a first logic state and a second logic state. A supply voltage is operably coupled to the asymmetric bi-stable latch, wherein upon application of the supply voltage to the asymmetric bi-stable CMOS latch is always set to the first logic state. A switch is operably coupled to the asymmetric bi-stable CMOS latch for changing the asymmetric bi-stable CMOS latch from the first logic state to the second logic state. Upon loss of the supply voltage and subsequent restoration of the supply voltage the asymmetric bi-stable latch returns to the first logic state to indicate that a loss of supply voltage has occurred.
The asymmetric bi-stable latch may further comprise a first CMOS inverter and a second CMOS inverter. The second CMOS inverter is cross-coupled to the first CMOS inverter. The first CMOS inverter is asymmetric with the second CMOS inverter.
The first CMOS inverter includes a first data node having a first nodal capacitance. The second CMOS inverter includes a second data node having a second nodal capacitance different from the first nodal capacitance which defines the asymmetry between the first CMOS inverter and the second CMOS inverter.
The symmetric bi-stable CMOS latch may further include a first inverter including a first p-channel field effect transistor, a first n-channel field effect transistor and a first data node located between the first p-channel field effect transistor and the first n-channel field effect transistor. A second inverter is provided including a second p-channel field effect transistor, a second n-channel field effect transistor and a second data node located between the second p-channel field transistor and the second n-channel field effect transistor. The first inverter is cross-coupled to the second inverter via a first coupling segment and a second coupling segment. The first p-channel field effect transistor is symmetric with the second p-channel field effect transistor. The first data node has a first nodal capacitance and the second data node has a second nodal capacitance asymmetric with the first nodal capacitance. The first p-channel field effect transistor and the second p-channel field effect transistor each have a source coupled to the supply voltage, wherein upon application of the supply voltage the latch is always set to the first logic state. The switch is coupled across the second n-channel field effect transistor for selectively switching the latch between the first logic state and the second logic state.
In one aspect, the switch includes a third n-channel field effect transistor. The switch is responsive to an input signal for switching the latch from the first logic state to the second logic state. The latch may further include a reset switch coupled between the first node and ground for selectively resetting the latch to the first logic state. The reset switch may include a fourth n-channel field effect transistor. In one preferred aspect, the first n-channel transistor has a drain area which is greater than the drain area of the second n-channel transistor.
In one aspect, the asymmetric bi-stable CMOS latch is SEU hardened. The asymmetric bi-stable CMOS latch includes an SEU hardening component.
In another embodiment, the present invention provides a method of operating a field programmable gate array. The method includes the step of defining a critical path logic circuit portion including an array of logic devices. A non-critical path logic circuit portion is defined including an asymmetric bi-stable CMOS latch having a first logic state and a second logic state. A supply voltage coupled to the asymmetric bi-stable latch is activated, to set the asymmetric bi-stable latch to the first logic state.
In one aspect, the method includes the step of defining the asymmetric bi-stable CMOS latch to include a first CMOS inverter and a second CMOS inverter cross-coupled to the first CMOS inverter. The first CMOS inverter is asymmetric with the second CMOS inverter. The method may further include the step of defining the first CMOS inverter to include a first data node having a first nodal capacitance, and the second CMOS inverter to include a second data node having a second nodal capacitance different from the first nodal capacitance which defines the asymmetry between the first CMOS inverter and the second CMOS inverter. The method further includes the step of defining the first CMOS inverter to include a first p-channel transistor and a first n-channel transistor, and the second CMOS inverter to include a second p-channel transistor and a second n-channel transistor, wherein the drain area of the first n-channel transistor is greater than the drain area of the second n-channel transistor.
In one aspect, the method includes the step of defining the asymmetric bi-stable CMOS latch as SEU hardened. The method may further include the step of defining the asymmetric CMOS bi-stable latch to include a first CMOS inverter, a second CMOS inverter cross-coupled to the first CMOS inverter by a first coupling segment and a second coupling segment, wherein the first CMOS inverter is asymmetric with the second CMOS inverter. The asymmetric bi-stable CMOS latch includes an SEU hardening component wherein the SEU hardening component includes positioning a thin film resistor in the first coupling segment.
The method may further include the step of reconfiguring the asymmetric CMOS bi-stable latch between the first logic state and the second logic state via a switch operably coupled to the asymmetric CMOS bi-stable latch. The switch may be defined to include an n-channel transistor. The method may further include the step of receiving a pulsed input signal by the n-channel transistor for switching the asymmetric bi-stable latch between the first logic state and the second logic state. The method may further include the step of resetting the asymmetric CMOS bi-stable latch to the first logic state via a reset switch operably coupled to the asymmetric CMOS bi-stable latch.